The present invention relates generally to a nonvolatile memory device and more specifically, to a technology of a test operation of a low power double-data-rate (LPDDR) nonvolatile memory device.
Generally, a memory device may be classified as a volatile memory device or a nonvolatile memory device. A nonvolatile memory device uses a nonvolatile memory cell and can preserve stored data even if a power source is off. The nonvolatile memory device includes a flash random access memory (RAM) and a phase change RAM (PCRAM).
A phase change memory device includes memory cells using a phase change material, for example, germanium antimony tellurium (GST), and is configured to store data in the memory cells by applying heat to the GST so that the GST has a crystal or amorphous status.
The nonvolatile memory device, such as a magnetic memory device and a phase change memory (PCM) device, has a data processing speed similar to that of a volatile RAM device.
Among nonvolatile memory devices, an LPDDR nonvolatile memory device is configured to perform an embedded operation such as a program operation or an erasure operation using an overlay window, as defined by Joint Electron Device Engineering Council (JEDEC). The overlay window includes a kind of software for supporting various nonvolatile memory devices to have the same LPDDRx interface and a circuit for supporting the software.
To perform the embedded operation in the LPDDR nonvolatile memory device, the overlay window must transmit a command signal, an address, and data through data (DQ) pins. However, when a non-embedded operation such as an active operation is performed, the command signal and the address are transmitted through address (CA) pins.
FIG. 1 illustrates a map of addresses in pre-active, active, read, and write operations in a conventional LPDDR nonvolatile memory device.
Referring to FIG. 1, a buffer address [1:0] is defined as two addresses of a0 and al, and a partition address [3:0] is defined as four addresses of b0˜b3. A row (X) address [12:0] is defined as thirteen addresses of c0˜12, and a column (Y) address [7:1] is defined as seven addresses of d1˜d7.
FIG. 2 illustrates an allocation table of CA pins depending on pre-active, active, read, and write commands in the conventional LPDDR nonvolatile memory device.
Referring to FIG. 2, command signals having a logic ‘high’ or ‘low’ state and the addresses defined in FIG. 1 are applied through the CA pins to the conventional LPDDR nonvolatile memory device.
FIG. 3 illustrates a mapping relationship of external addresses, logical addresses, and DQ pins in the conventional LPDDR nonvolatile memory device.
Referring to FIG. 3, 26 addresses are allocated to the external addresses, that is, command addresses. Among these addresses, the external addresses [4:2] represent a read/write operation command, the external addresses [19:5] represent an active command, and the external addresses [25:20] represent a pre-active command.
The external addresses [8:2] are defined as column (Y) addresses of the logical addresses, the external addresses [21:9] are defined as row (X) addresses of the logical addresses, and the external addresses [25:22] are defined as partition addresses of the logical addresses.
The external addresses [15:0] are defined as 16 DQ pins DQ0_R˜DQ15_R, and the external addresses [25:16] are defined as 10 DQ pins DQ0_F˜DQ9_F. Among DDR data, data inputted at a rising edge of a DQ strobe signal are input through the DQ pins DQ0_R˜DQ15_R, and data inputted at a falling edge of the DQ strobe signal DQS are input through the DQ pins DQ0_F˜DQ9_F.
FIG. 4 illustrates command signals and addresses that are input through DDR CA pins in a double data rate synchronous DRAM device and a nonvolatile memory device. A detailed explanation for FIG. 4 will be omitted because it is described in the specifications of the JEDEC.
FIG. 5 illustrates the problem of data collision that occurs when an address driving unit is coupled with a command driving unit in a device supporting the specifications of an LPDDR2 nonvolatile memory device with analysis equipment.
In general, in a DDR2 device, an address is input in synchronization with a rising edge and a falling edge of a clock CLK. Thus, two or less address driving units are coupled to each DQ pin and five or less address driving units are coupled to each CA pin.
An operation of receiving an address is explained using, for example, a CA pin CA1. Referring to FIGS. 1 to 4, an address c12 (a21) is input to the CA pin CA1 when the pre-active command is input, an address d5 (a6) is input to the CA pin CA1 when the active command is input, and an address driving unit corresponding to an address d3 (a4) is coupled to the CA pin CA1 when the read or write command is input.
In an active mode, a signal input on a rising edge line of the CA pin CA1 is a logic ‘high’ signal corresponding to the command signal. The logic ‘high’ signal applied to a command driving unit is coupled to a falling edge line of the CA pin CA1 as shown in a path (A). The falling edge line of the CA pin CA1 is coupled through a rising edge line of a DQ pin DQ4 to a falling edge line of the DQ pin DQ4, a falling edge line of the CA pin CA0 and a rising edge line of the CA pin CA0, which results in data collision with a command driving unit of the CA pin CA0. Such data collision occurs because the LPDDR nonvolatile memory device should transmit an address through a data pin as well as an address pin for supporting the embedded operation.
As a result, the usage of the analysis equipment is limited, and test time increases, which increases the costs required to test the LPDDR nonvolatile memory device. For example, if a buffered program is performed through the LPDDR nonvolatile memory, information is transmitted using a command code, an address, a program buffer, a multi-purpose register, and an execute command. In the program operation, a time t0W for writing data in the overlay window and a write time tPGM for programming the data in a cell are required. The time t0W is (tRP+tRCD+tWR)×(4+data count/8), wherein tRP represents a RAS precharge time, tRCD represents a RAS to CAS delay, and tWR represents a write recovery time. In a DDR device that uses eight clocks, the condition for writing the data in the overlay window sets a burst length to ‘16’, tRP to 3×tCK, tRCD to 100 nsec, and tWR to write latency (WL)+BL/2.
That is, in the buffered program operation, all of the above information is required to perform the embedded operation. The information is transmitted into the memory using the write command. As a result, as the information required in the program operation becomes greater, the write operation time becomes longer. Moreover, when the information is dispersed in the overlay window, a pre-active operation and an active operation are required. The number of required pre-active and active operations is 4+data count/8. The data count is determined depending on how many bytes of data are written in the cells, and represents the number of bytes of data transmitted into the program buffer.
The write time of the overlay window corresponds to hundreds of nanoseconds. That is, hundreds of nanoseconds are s required only for setting the program operation. Since the time taken to program the data of 4 bytes in the cells is about hundreds of nanoseconds (e.g., 100 nsec), the write time of the overlay window is a relatively long time.
FIG. 6 illustrates a block diagram of a conventional nonvolatile memory device.
The conventional nonvolatile memory device includes an overlay window 10, a command decoder 20, an address decoder 30, and a global input output bus (WGIO) 40.
The overlay window 10 includes a command code storage region 11 configured to store a command code, a command address storage region 12 configured to store a command address, a command data storage region 13 configured to store command data and a program buffer 14.
The command code stored in the command code storage region 11 is decoded by the command decoder 20 and then transmitted into a memory (not shown). The command address stored in the command address storage region 12 is decoded by the address decoder 30 and then transmitted into the memory.
The command data stored in the command data storage region 13 is transmitted through the global input output bus 40 into the memory. Program information buffered by the program buffer 14 is transmitted through the global input output bus 40 into the memory.
The conventional nonvolatile memory device designates an address of the overlay window 10 using an address input through a CA pin. A DQ pin transmits data applied from the outside into the overlay window 10. The data input through the DQ pin is stored in the command code storage region 11, the command address storage region 12, the command data storage region 13, and the program buffer 14. As a result, a command signal, an array address, and cell data for the memory are determined based on values stored in the overlay window 10. Then, when an execute command is applied, the embedded operation is performed.
The above-described problems result from the usage of the overlay window 10 to transmit a command signal, an address, and a data in a test operation of the LPDDR nonvolatile memory device.